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Decoder with the Dynamic CMOS Matrix

PALOČKO, L., BROULÍM, J., MOLDASCHL, J. Decoder with the Dynamic CMOS Matrix. In 21st Telecommunications Forum TELFOR 2013. Bělehrad: IEEE, 2013. s. 612-615. ISBN: 978-1-4799-1419-7
Jazyk publikace: eng
Anglický název: Decoder with the Dynamic CMOS Matrix
Rok vydání: 2013
Místo konání: Bělehrad
Název zdroje: IEEE
Autoři: Ing. Lukáš Paločko , Ing. Jan Broulím , Ing. Jan Moldaschl ,
Abstrakt EN: This paper presents the Full Custom Design technique in the IC digital design, which is used to achieve the maximum performance or minimum power. The technique was applied on the decoder of the ARM1 register file. Presented research combines a static CMOS logic and a dynamic logic, which has higher speed than the equivalent static family. The validation of the design is made by the SPICE3 simulator (BSIM3 model) considering RC parasitic values of metal wiring. Our results demonstrate the size of the register file decoder and behavior of the dynamic matrix.
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