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Fully parallel FPGA decoder for irregular LDPC codes

Citace:
BROULÍM, J., BROULÍM, P., MOLDASCHL, J., GEORGIEV, V., ŠALOM, R. Fully parallel FPGA decoder for irregular LDPC codes. In Proceedings of Papers : 2015 23rd Telecommunications Forum (TELFOR 2015). Piscataway: IEEE, 2015. s. 309-312. ISBN: 978-1-5090-0055-5
Druh: STAŤ VE SBORNÍKU
Jazyk publikace: eng
Anglický název: Fully parallel FPGA decoder for irregular LDPC codes
Rok vydání: 2015
Místo konání: Piscataway
Název zdroje: IEEE
Autoři: Ing. Jan Broulím , Ing. Pavel Broulím , Ing. Jan Moldaschl , Doc. Dr. Ing. Vjačeslav Georgiev , Ing. Radek Šalom ,
Abstrakt EN: One of the most significant current discussions in error correction coding is on the replacement of state-of-the- art codes by new innovative solutions. We propose a scalable parallel FPGA architecture for LDPC decoding. Regular and irregular codes are supported by the presented architecture. The architecture can be easily utilized in hardware applications. The performance of synthetized decoders is presented.
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